The shrinking of the field-effect device channel length requires an increase in the capacitance of the gate dielectric in order to achieve desired performance. There are difficulties associated with decreasing the oxide thickness in a reproducible fashion when that gate dielectric is SiO2. Leakage currents are unacceptable when the oxide thickness is less than 1.2 nm. An alternative approach has been to deposit high-k dielectrics. However, a difficulty with this approach is that, in general, these materials are mismatched with the underlying silicon lattice. This leads to formation of additional interface states, which degrades the device performance. These relatively high dielectric material display temperature sensitivity with respect to micro-crystal formation, migration phenomenon, and relatively low intrinsic dielectric constants. In addition, these materials are not easy to alter or modify.